Infineon Retains HyperRAM Related – EETimes

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Nothing says enduring like a know-how that’s weathered mergers and acquisitions.

Infineon Applied sciences’ newest iteration of its HyperRAM growth reminiscence can hint its roots again to Spansion, which merged with Cypress Semiconductor in late 2014. First introduced in early 2015 as a companion RAM system, HyperRAM was designed to be used in systems-on-chip (SoCs) and microcontrollers (MCUs), the place each RAM and flash are linked to the identical HyperBus interface; growth of the preliminary HyperRAM know-how was knowledgeable by the prior work on HyperBus and HyperFlash applied sciences.

Because the debut of HyperRAM, applied sciences and use circumstances have developed, though the IoT has been a driving power for lower-power reminiscence innovation over the previous decade. With HyperRAM 3.0, Infineon is aiming the high-bandwidth, low-pin–depend pSRAM-based risky reminiscence at functions requiring growth RAM reminiscence, together with video buffering, manufacturing unit automation, automotive vehicle-to-everything (V2X), and what it calls the bogus intelligence of issues (AIoT), mentioned Shivendra Singh, lead principal engineer for the corporate’s HyperRAM merchandise. It’s additionally helpful for any utility that wants scratch-pad reminiscence and information buffering for intense mathematical calculations, together with embedded methods.

Infineon is positioning HyperRAM as a high-throughput, low-power growth reminiscence resolution for high-performance embedded methods and various to SRAM, pSRAM, and DRAM. (Supply: Infineon)

An enormous promoting level of HyperRAM when it was first launched was its low pin depend, which is why it’s superb for IoT and automotive use circumstances and SoCs and MCUs—a smaller package deal saves cash, permitting for cost-optimized designs as a result of the elevated per-pin information throughput of the HyperBus interface makes it potential to make use of MCUs with fewer pins and PCBs with fewer layers.

The small-footprint, low-pin–depend interface reduces design complexity however not on the expense of efficiency, Singh mentioned.

HyperRAM performs higher than present applied sciences out there, resembling pSRAMs and SDR DRAMs, with a far increased throughput per pin whereas staying environment friendly from energy consumption perspective.

“Energy consumption is one other key attraction for a majority of the use circumstances,” he mentioned, whether or not it’s saving energy or enhancing the system battery life; energy consumption is a priority on the edge, particularly as units develop into inherently smarter—the AIoT.

HyperRAM 3.0 has seen some will increase in densities because the know-how was first launched with 512 Mb, now accessible on the excessive finish. Help for the brand new prolonged HyperBus interface allows 800-MB/s information charges. Each are AEC-Q100–certified and assist industrial and automotive temperature grades as much as 125˚C; HyperRAM 3.0 is now accessible in a BGA-49 package deal.

There was a big hole between the primary and second iterations of HyperRAM: Model 2.0 was launched in 2021 with assist for each the Octal xSPI and HyperBus JEDEC–compliant interfaces with information charges of as much as 400 MB/s. The authentic 64Mb HyperRAM communicated on the identical velocity as HyperFlash, with a learn throughput of as much as 333 MB/s and 36-ns array learn/write latency.

By combining them on the HyperBus interface, complete pin depend could possibly be lowered from about 40 to 12. Though a decrease pin depend may imply a smaller package deal, the scale discount may differ relying on the use case and any desired extra features and options.

A typical use case for HyperRAM 3.0 may for be graphics/show methods or edge AI processing in an industrial setting utilizing a 49-ball BGA measuring 8 × 8 mm with a density of 256 Mb with 16-bit information bus width—Singh mentioned Infineon has been in a position to double the info fee with out rising the clock velocity.

Typical use circumstances for HyperRAM are graphics/show methods and edge AI processing within the industrial and shopper segments. (Supply: Infineon)

HyperRAM is filling the hole between DDR4/DDR5 DRAM, which is getting more and more complicated, whereas DDR3 and beneath are in upkeep mode, he added. “DDR distributors are transferring towards the upper know-how node, increased efficiency, and better density.”

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