JOB: DDR Lead Verification Engineer at Cadence

Location: Bengaluru and Pune

Firm: Cadence

Place Description:

  • Useful Verification Engineer for DDR Reminiscence Controller and PHY IP growth crew.
  • The place relies in Bangalore.
  • The position would come with useful verification of the DDR Reminiscence Controller and PHY IP resolution of Cadence.
  • The work concerned will likely be working with the prevailing useful verification surroundings, the addition of latest options into the verification surroundings, making certain numerous buyer configurations are clear as a part of verification regressions, supporting prospects in case of any points with utilizing the verification surroundings, and useful and code protection.
  • The engineer can be accountable to make sure that the design is according to the technical and high quality necessities set for the crew – notably with respect to useful and code protection.

Place Necessities:

    • BE/BTech/ME/MTech – Electrical / Electronics / VLSI with expertise as a design and verification engineer, with a big portion of the current work expertise on verification surroundings growth.
    • Sturdy background in useful verification fundamentals, surroundings planning, take a look at plan era, and surroundings growth is a should.
    • System Verilog expertise and expertise with UVM-based useful verification surroundings growth are required.
    • Prior RTL Design expertise utilizing Verilog is a should – in order that the verification engineer is self-sufficient for many features of debugging.
    • The Newest DDR Protocol expertise is extremely fascinating. Prior expertise in useful verification and debugging of advanced protocols is a should.
    • AXI3/4 expertise is fascinating.
    • Prior expertise in IP growth groups can be an added benefit.

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